1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, which is suited to the formation of wiring patterns and the like in semiconductor devices, and to a method of forming a pattern.
2. Description of the Related Art
In recent years, the trends toward making wires finer, increasing the number of layers, and the like have intensified in the manufacture of semiconductor integrated circuits in order to achieve greater integration, higher speeds, and the like. In semiconductor devices, there has been the trend toward increasing the aspect ratio of wires in order to prevent an increase in the resistance of the wires due to the wires being made to be finer. When the number of layers having wires of high aspect ratios is increased, the steps on the substrate become large. However, with a substrate having large steps, it is not possible to form a fine resist pattern.
Thus, there has been disclosed a three-layer resist process which can form a fine resist pattern on a substrate having large steps (refer to, for example, Journal of Vacuum Science Technology. (November/December 1979). vol. 16, no. 6. pp. 1620-1624). In this three-layer resist process, first, an innermost layer (lower layer) is formed by coating and hardening a thermosetting resin on an target to be worked formed on a substrate. The steps on the substrate are leveled by the innermost layer (lower layer). Then, an inner layer (intermediate layer) formed of Si-containing material, which exhibits oxygen plasma etching resistance, is formed on the innermost layer (lower layer). Next, a photosensitive resin is coated on this inner layer (intermediate layer) so as to form a surface layer (upper layer). The surface layer (upper layer) is patterned by being exposed, developed, and the like. Next, the inner layer (intermediate layer) is patterned by etching using the pattern of the surface layer (upper layer) as a mask. Then, the innermost layer (lower layer) is patterned by etching using the pattern of the inner layer (intermediate layer) as a mask. As a result, a three-layer resist pattern having a high aspect ratio is obtained. Then, the target to be worked on the substrate is patterned by etching using this three-layer resist pattern as a mask, and the desired wiring pattern is formed. In this three-layer resist process, patterning of a photosensitive resin layer, which serves as the surface layer (upper layer) on the inner layer (intermediate layer) formed on a relatively thick the innermost layer (lower layer), is carried out. Thus, patterning is not affected by the steps on the substrate, and it is possible to obtain a fine pattern with a high aspect ratio and no variations in dimensions.
In this conventional three-layer resist process, a silicon-containing material is used as the inner layer (intermediate layer), and generally, SOG (spin-on glass) is used (refer to, for example, Japanese Patent Application Laid-Open (JP-A) No. 04-005658). Because the SOG is transparent material, during patterning of the surface layer (upper layer), there is high reflectance of light which is irradiated from a direction of the surface layer (upper layer). A problem arises in that high-performance and accurate patterning of the surface layer cannot be carried out due to the interference of the light reflected by the innermost layer.
Moreover, there are cases in which an electron beam is used at the time of patterning the surface layer (upper layer). However, in these cases, problems arise in that the manufacturing costs are high, and the like (refer to, for example, JP-A No. 60-254034 and JP-A No. 05-265224).
On the other hand, in order to accurately transfer the resist pattern of the surface layer (upper layer) to the inner layer (intermediate layer), the inner layer (intermediate layer) must be formed as a thin layer of about 80 nm to 150 nm. In a case in which the inner layer (intermediate layer) is formed to be thick, a problem arises in that even the inner layer (intermediate layer) is affected and deteriorates when the surface layer (upper layer) is damaged and the configuration thereof deteriorates. On the other hand, when the inner layer (intermediate layer) is formed to be thin, it is easy for defects to arise at the inner layer (intermediate layer). For example, when the innermost layer (lower layer) is formed of a resin which contains an additive, a problem arises in that it is easy for pin holes to arise in the mask patterned formed by the inner layer (intermediate layer). When etching of the innermost layer (lower layer) is carried out by using a mask pattern in which pin holes have arisen, defects caused by the pin holes arise in the formed pattern of the innermost layer (lower layer), and there is the problem that it is not possible to carry out high-performance and accurate patterning.
Accordingly, a demand has been made on that a method of forming a pattern and a method of manufacturing a semiconductor device, which can conveniently and in fine accurate form a fine pattern of a high aspect ratio without such problems.